1. Field of the Invention
An aspect of the present invention relates to a semiconductor storage apparatus capable of electrically rewriting data, and more particularly to a nonvolatile semiconductor storage apparatus among semiconductor storage devices.
2. Description of the Related Art
A surge has a risen in a demand for a compact, large-capacity nonvolatile semiconductor storage device, and NAND flash memory which can be expected to realize higher integration and greater capacity has gained attention. Under a common manufacturing method, difficulty has become encountered in miniaturizing a design rule for microprocessing a trace pattern, or the like.
For these reasons, in order to enhance the integration of memory, a plurality of semiconductor storage devices including three-dimensionally arranged memory cells have recently been proposed (for example, refer to JP-2003-078044-A, U.S. Pat. No. 5,599,724, U.S. Pat. No. 5,707,885 and Masuoka et al., “Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEEE TRANSACTIONS ON ELECTRONIC DEVICES, VOL. 50, NO. 4, pp 945-951, April 2003).
In many related-art semiconductor storage devices including three-dimensionally arranged memory cells, memory cells must be subjected to processing pertaining to a plurality of photo engraving processes (hereinafter abbreviated as “PEP,” wherein patterning is performed through processes, such as a lithography process and an etching process, employing a so-called photoresist) on a per-layer basis. A PEP which is performed at a minimum line width of the design rule is taken as a “critical PEP,” and a photo engraving process which is performed at a line width greater than the minimum line width of the design rule is taken as “rough PEP.” In a related-art semiconductor storage device in which memory cells are arranged in a three-dimensional pattern, three critical PEPs or more are required for one layer of memory cell. Moreover, in many semiconductor storage devices, memory cells are simply stacked one on top of the other, which unavoidably results in an increase in cost attributable to three-dimensional integration of memory cells.
Additionally, in a case where the memory cells are arranged in a three-dimensional pattern, a cost reduction effect can be enhanced if all via holes for a plurality of word-line electrode layers (such as, a polysilicon layers, an amorphous silicon layers or metal layers) of the memory cells can be formed in one process.